1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device, and more particularly to a non-volatile semiconductor memory device such as a flash electrically erasable programmable read only memory (EEPROM) in which a writing operation and an erasing operation can be electrically performed.
2. Description of the Related Art
In a conventional non-volatile semiconductor memory device such as a flash EEPROM memory in which memory data stored in memory cells can be collectively and electrically erased, there is a problem in that the memory cells are sometimes over-erased during an initializing operation because of the memory structure and the erasing method using tunneling of electrons so that the threshold voltage of the over-erased memory cell becomes negative, that is, the over-erased memory cell is set to the depletion state.
In order to solve this problem, as disclosed in, for example, Japanese Laid Open Patent Disclosure (JP-A-Heisei 4-228193), before the memory cells are collectively initialized in an initializing operation, a pre-programming operation is performed to all the memory cells so that electrons are injected to a floating gate. Thus, the threshold voltage of the floating gate before an erasing operation is started is made to be almost a uniform value of equal to or more than 7 V. Then, a high voltage is applied between the gate and source of a transistor of each of the memory cells to pull out the electrons which are accumulated in the floating gate, using the Fowler-Nordheim tunneling phenomenon. In this manner, the erasing operation of the flash EEPROM is performed.
In the above-mentioned initializing operation, the following method is employed in order to prevent the memory cells from being erased more than necessary, i.e., from being over-erased. That is, the pulse width of the high voltage pulse (hereinafter, to be referred to as "erasure pulse") which is applied to a source line of a transistor of the memory cell for the erasure is made shorter than the pulse width which is necessary to erase the memory cell. Every time the erasure pulse with this short pulse width is applied to the source line, the memory data of all the memory cells in the memory cell array are read out. Then, it is determined whether or not the memory data of all the memory cells in the memory cell array are erased so that the memory cells are in the erasure state. If one or more of the memory cells are not in the erasure state, the erasure pulse with the short pulse width is applied to the source line once again. A test operation which is referred to as an "erasure verifying" operation is performed to determine whether or not the memory data of all the memory cells are erased. This operation is also referred to as an "erasure test I". Such an erasure verifying operation and the application of the erasure pulse to the source line are repeated until all the memory cells in the memory cell array are set to the erasure state.
After the memory data of all the memory cells are erased, it is determined whether or not any over-erased memory cell exists. This operation is referred to as an "erasure test II". When all the memory cells in the memory cell array are not in an over-erased state, the data indicative of completion of the initializing operation is outputted from the non-volatile semiconductor memory device.
On the other hand, if any of the memory cells is in the over-erasure state, the pre-programming operation is performed with a low gate voltage to the memory cells which are connected to the bit line to which the over-erased memory cell is connected, so that the threshold voltages of the memory cells are written backed to the levels capable of performing the normal reading operation. Then, the erasure verifying operation 2 (referred to as an "erasure test III") is performed once again from a potential slightly higher than the potential with which erasure verifying operation 1 (erasure test I) is performed. When all the memory cells are in the erasure state, the data indicative of completion of the initializing operation is output from the non-volatile semiconductor memory device.
In the flash EEPROM, the initializing operation of pre-programming operation, erasing operation, erasure tests I, II, and III are automatically performed in response to an initializing instruction.
FIG. 1 is a block diagram illustrating the structure of a conventional non-volatile semiconductor memory device. Referring to FIG. 1, the conventional non-volatile semiconductor memory device is composed of a memory array 312, an address buffer 306, an X address decoder 311, a Y selection transistor group 310, a sense amplifier 309, an I/O buffer 307, a write circuit 308 and a control circuit 313. The memory array 312 stores data. The address buffer 306 inputs an external address signal and outputs an internal address signal. The X address decoder 311 selects one of word lines W1 to Wn based on the internal address signal outputted from the address buffer 306. The Y selection transistor group 310 selects one of bit lines based on the internal address signal. The sense amplifier 309 amplifies data read from the memory cell which is selected by the X address decoder 311 and the Y selection transistor group 310. The I/O buffer 307 outputs the output of the sense amplifier 309 to a data input/output pin 301. The write circuit 308 writes a data inputted from the data input/output pin 301 in the memory cell which is selected by the X address decoder 311 and the Y selection transistor group 310. The control circuit 313 inputs a chip enable signal, an output enable signal and a power supply voltage Vpp for the data writing operation and generates internal control signals for controlling the operation of address buffer 306, X decoder 311, Y selection transistor group 310, sense amplifier 309, write circuit 308, and I/O buffer 307 output.
FIGS. 2A and 2B are flow chart illustrating the operation of the conventional non-volatile semiconductor memory device. Referring to FIGS. 2A and 2B, when an automatically initializing instruction is inputted (Step 802), the data of 00.sub.H (hexadecimal notation) is written in all the memory cells, i.e., is pre-programmed (Steps 804, 806 and 808). After the data of "00".sub.H is written in the last address (Yes in Step 806), an erasing operation is performed.
In the erasing operation, the pulse width of an erasure pulse which is applied to the source line for the memory cell erasure is made shorter than the pulse width which is actually necessary to erase the memory cell. Each time the erasure pulse with this short pulse width is applied to the source lines once, the memory data of all the memory cells in the memory cell array 312 is read out to determine whether or not the memory data of all the memory cells in the memory cell array 312 are set to an erasure state (Steps 810, 812, 816, and 818). In the erasure test I (step 812) determining whether or not the memory cells are set to the erasure state, when it is determined that there is any erasure failed memory cell, the number of times Ne1 of application of the erasure pulse is incremented by "1" Ne1=Ne1+1, and it is determined whether the number of times Ne1 is larger than a predetermined value (Step 814). When it is determined that the number of times Ne1 is larger than the predetermined value, the memory device is determined to be in the initialization failure state. When it is determined that the number of times Ne1 is not larger than the predetermined value, the erasure pulse is applied to the memory device again in the step 810.
When it is determined that all the memory cells are correctly erased (Step 816), i.e., after the test reaches the last address, the erasure test II determining whether or not there is any over-erased memory cell is performed (Steps 819, 820 and 822). When it is determined that there is any over-erased memory cell (Step 819), a soft write operation, i.e., a write operation of data in the over-erased memory cell with a low gate voltage is performed (Step 824). Then, the erasure test II is performed (Step 826). When it is determined in the step 826 that there is still an over-erased memory cell, the number of times Ne2 is incremented by "1", i.e., Ne2=Ne2+1, and then it is determined whether the number of times Ne2 is larger than a predetermined value (Step 828). When it is determined in the step 828 that the number of times Ne2 is larger than the predetermined value, it is determined that the memory device is in the initialization failure state. On the other hand, when it is determined in the step 828 that the number of times Ne2 is not larger than the predetermined value, the soft write operation is performed again in the step 824.
Then, after the erasure test II is ended, the erasure test III is performed (Steps 834, 836 and 838). When it is determined during the erasure test III that any memory cell is in the failure state, it is determined that the memory device is in the initialization failure state.
When the erasure test III is passed, a status polling operation is performed to read the state of the memory cells (Step 840) and then the initialize mode is reset (Step 842).
In this manner, the automatically initializing operation is ended.
In the conventional automatically initializing operation, there is a problem in that there are electrons which can not be pulled out from the floating gate while the erasing operation is performed or electrons which can not be injected into the floating gate while the write operation is performed. Thus, these electrons are trapped in a tunneling oxide film (these electrons are referred to as "trapped electrons") and there is a problem that these electrons deteriorate the erasure and write characteristics.
Also, when a high voltage is applied to the source of the memory cell for erasure, holes are trapped in the tunnel oxide film (these holes are referred to as "trapped holes"). There is another problem in that the trapped holes cause data holding failure which is a fatal error to the read only memory (ROM).